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Old 09-13-2017, 08:22 AM   #1081
Urwumpe
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 Are you implementing Electrical systems?
Later. Some basic things are already existing there, but what he means are the 1 Mbit/s serial data busses (very similar to MIL-STD-1553) called Shuttle Bus, which connect the various MDMs and bigger subsystems to the GPCs.

What could be interesting about the electrical systems -for the bigger relays and switches, we have the specifications, including how fast they react.
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Old 09-13-2017, 08:59 AM   #1082
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Wow nice
So you are planning on which busses specifically ?
Flight critical, payload, Ldb ?

Very nice to see all the nice coming stuff, great work
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Old 09-13-2017, 09:04 AM   #1083
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 Wow nice
So you are planning on which busses specifically ?
Flight critical, payload, Ldb ?

Very nice to see all the nice coming stuff, great work
Not specifically - I focus on having the C++ components to do all Shuttle busses and the simpler serial data buses used to connect subsystems to the MDMs.

Implementing and connecting the subsystems to the MDMs or writing the software to use the buses is second priority for me... first I'll finish the basic infrastructure. One of the tougher aspects right now is that it is the second time I try multi-threading in Orbiter.
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Old 09-13-2017, 09:13 AM   #1084
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Ah ok I see, not specifically bus with GPC interaction, but the whole stuff behind and MDM connection to systems.

That's a hell of a project

I was wondering, is it possible to have some updates of what you have added in the SSU 5 , and what you are planning to do? ( if it's not secret of course )
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Old 09-13-2017, 10:42 AM   #1085
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 I was wondering, is it possible to have some updates of what you have added in the SSU 5 , and what you are planning to do? ( if it's not secret of course )
Mostly I plan to have a SSU 5.

Seriously though: This is team effort, everyone has his own pet topic he likes to push forward and everyone also does some of the necessary work that nobody really likes.

Personally, I would like to find the time getting EVA capability back into SSU for SSU 5. But right now, I can't even tell when I will have all bugs ironed out in the new GPC model.
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Old 09-13-2017, 11:56 AM   #1086
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Ahah

New GPC model? Very interesting.
More DPS pages and Major Function? Or deep re writing of the system behind?
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Old 09-13-2017, 12:11 PM   #1087
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 More DPS pages and Major Function? Or deep re writing of the system behind?
The latter in first place, but once I have this done, we can also resume adding more display formats.

Right now, we sort of ignore the GPCs and other hardware and simply run the software. We have no memory configuration, no tape drive, essentially everything that influences the runtime behavior is missing.

Design goal right now is switching to a partition model. A partition as in computing - multiple GPCs running the same software are treated as if they are one big computer. Additionally, I am using multi-threading now, so the GPC software can be written like it is described in the STS software documentation, without caring about Orbiters time step model or frame rates. Just one big function, if you like to. The only thing that really synchronizes with Orbiters simulation is the Virtual IOP. If you pause Orbiter, the GPC software can run for a few microseconds before stopping at an IO operation.

The GPCs are then just "execution resources" for the partition.

Another factor for rewriting the core DPS there: We can have a better BFS then.
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Old 09-13-2017, 12:33 PM   #1088
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 Another factor for rewriting the core DPS there: We can have a better BFS then.
Fixed.
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Old 09-13-2017, 12:49 PM   #1089
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 Fixed.
Sorry. I wanted to be diplomatic there.
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Old 09-13-2017, 12:59 PM   #1090
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Ahah

Ok thanks for the info.
So it's quite a deep GPC rewritting you re on
Is it like almost emulation of the GPC soft?
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Old 09-13-2017, 01:30 PM   #1091
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 Is it like almost emulation of the GPC soft?
No. Not even slightly. I replicate some HAL/S high-level language features which connect directly to the FCOS of PASS. That is really all. Also I plan reproducing the display macros of HAL/S in C++ for easier writing of display software.

There are some attempts at emulation at times, but we lack information about the AP-101S there and we gain little accuracy there. We just don't need to fake the register contents then for one OPS 0 display.

And on the other hand - native C++ implementation of the software should be way faster even than just-in-time compiled AP-101S machine code.

And BTW: We can already enjoy enough low-level programming with the VirtualIOP then.

Last edited by Urwumpe; 09-13-2017 at 01:39 PM.
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Old 09-13-2017, 05:04 PM   #1092
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It looks like a nice plan

What is exaclty VirtualIOP?
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Old 09-13-2017, 05:59 PM   #1093
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 It looks like a nice plan

What is exaclty VirtualIOP?
Each GPC has an Input/Output processor (IOP), which is essentially a special computer that can communicate with the Shuttle busses.

Since we are reducing the GPCs to a single partition in the usual case, we don't need four IOPs for example, but one virtual IOP for the whole partition, that behaves like a single IOP for the software, but maps to the actual IOP hardware for talking to the busses.

More joy: There is actually even a tiny virtual CPU layer around. But you never talk to it directly, it is hidden in the FCOS implementation. We just need it for implementing the BFS, because the BFS has no FCOS.
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Old 09-18-2017, 04:12 PM   #1094
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 Time to make decisions without data (a.k.a. most days in SSU ):
{image}
Any objections if I consider the "post-liftoff water" portion of the SSWS to be only the water being sprayed onto the pad surface, around the SRB holes? (and the water inside the flame holes would be the "pre-liftoff water")
Well... it looks like the SLC-6 SSWS valves all feed into one pipe (instead of 2 at LC39) which then feeds the launch mount, which means there is not "post-liftoff water".
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Old 09-18-2017, 04:42 PM   #1095
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Little SSU work here thanks to a lot of official paperwork...

But I wonder the following: Is the optimization for a partition oriented DPS really needed, if we have multithreading? A lot of the work is about hiding the right amount of hardware from the software and abstract the FCOS properly.

Now, would we allow five GPCs executing the software parallel, we would have to solve the full synchronization issues between the GPCs and more CPU load, but the FCOS abstraction could be done simpler. Debugging the actual PASS software would be more difficult, but the DPS rewrite could be done faster.
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